From: "Nícolas F. R. A. Prado" <[email protected]>
To: Matthias Brugger <[email protected]>
Cc: "AngeloGioacchino Del Regno"
<[email protected]>,
[email protected],
"Nícolas F. R. A. Prado" <[email protected]>,
"Krzysztof Kozlowski" <[email protected]>,
"Rob Herring" <[email protected]>,
[email protected], [email protected],
[email protected], [email protected]
Subject: [PATCH] arm64: dts: mt8192: Follow binding order for SCP registers
Date: Tue, 3 May 2022 17:25:31 -0400 [thread overview]
Message-ID: <[email protected]> (raw)
The dt-binding for SCP documents the reg-names order as sram, cfg,
l1tcm. Update the SCP node on the mt8192 devicetree to follow that
order, which gets rid of a dtbs_check warning. This doesn't change any
behavior since the SCP driver accesses the memory regions through the
names anyway.
Signed-off-by: Nícolas F. R. A. Prado <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 26dbe9ecc528..733aec2e7f77 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -699,9 +699,9 @@ spi7: spi@1101e000 {
scp: scp@10500000 {
compatible = "mediatek,mt8192-scp";
reg = <0 0x10500000 0 0x100000>,
- <0 0x10700000 0 0x8000>,
- <0 0x10720000 0 0xe0000>;
- reg-names = "sram", "l1tcm", "cfg";
+ <0 0x10720000 0 0xe0000>,
+ <0 0x10700000 0 0x8000>;
+ reg-names = "sram", "cfg", "l1tcm";
interrupts = <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&infracfg CLK_INFRA_SCPSYS>;
clock-names = "main";
--
2.36.0
next reply other threads:[~2022-05-03 21:25 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-03 21:25 Nícolas F. R. A. Prado [this message]
2022-05-04 8:10 ` [PATCH] arm64: dts: mt8192: Follow binding order for SCP registers AngeloGioacchino Del Regno
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