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From: Nancy.Lin <[email protected]>
To: Rob Herring <[email protected]>,
	Matthias Brugger <[email protected]>,
	Chun-Kuang Hu <[email protected]>,
	"Philipp Zabel" <[email protected]>,
	<[email protected]>,
	"AngeloGioacchino Del Regno"
	<[email protected]>, <[email protected]>
Cc: [email protected],
	[email protected],
	Yongqiang Niu <[email protected]>,
	David Airlie <[email protected]>,
	"jason-jh . lin" <[email protected]>,
	[email protected], [email protected],
	Nick Desaulniers <[email protected]>,
	[email protected], [email protected],
	Nathan Chancellor <[email protected]>,
	"Nancy . Lin" <[email protected]>,
	[email protected],
	[email protected]
Subject: [PATCH v20 09/25] soc: mediatek: mmsys: add mmsys for support 64 reset bits
Date: Wed, 4 May 2022 17:14:24 +0800	[thread overview]
Message-ID: <[email protected]> (raw)
In-Reply-To: <[email protected]>

Add mmsys for support 64 reset bits. It is a preparation for MT8195
vdosys1 HW reset. MT8195 vdosys1 has more than 32 reset bits.

1. Add the number of reset bits in mmsys private data
2. move the whole "reset register code section" behind the
"get mmsys->data" code section for getting the num_resets in mmsys->data.

Signed-off-by: Nancy.Lin <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Reviewed-by: CK Hu <[email protected]>
---
 drivers/soc/mediatek/mtk-mmsys.c | 39 ++++++++++++++++++++------------
 drivers/soc/mediatek/mtk-mmsys.h |  1 +
 2 files changed, 26 insertions(+), 14 deletions(-)

diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 43bb8026e6d5..417f2520be58 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -20,6 +20,8 @@
 #include "mt8195-mmsys.h"
 #include "mt8365-mmsys.h"
 
+#define MMSYS_SW_RESET_PER_REG 32
+
 static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
 	.clk_driver = "clk-mt2701-mm",
 	.routes = mmsys_default_routing_table,
@@ -86,6 +88,7 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
 	.routes = mmsys_default_routing_table,
 	.num_routes = ARRAY_SIZE(mmsys_default_routing_table),
 	.sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
+	.num_resets = 32,
 };
 
 static const struct mtk_mmsys_match_data mt8173_mmsys_match_data = {
@@ -100,6 +103,7 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
 	.routes = mmsys_mt8183_routing_table,
 	.num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
 	.sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
+	.num_resets = 32,
 };
 
 static const struct mtk_mmsys_match_data mt8183_mmsys_match_data = {
@@ -114,6 +118,7 @@ static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
 	.routes = mmsys_mt8186_routing_table,
 	.num_routes = ARRAY_SIZE(mmsys_mt8186_routing_table),
 	.sw0_rst_offset = MT8186_MMSYS_SW0_RST_B,
+	.num_resets = 32,
 };
 
 static const struct mtk_mmsys_match_data mt8186_mmsys_match_data = {
@@ -287,13 +292,19 @@ static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned l
 {
 	struct mtk_mmsys *mmsys = container_of(rcdev, struct mtk_mmsys, rcdev);
 	unsigned long flags;
+	u32 offset;
+
+	offset = (id / MMSYS_SW_RESET_PER_REG) * sizeof(u32);
+	id = id % MMSYS_SW_RESET_PER_REG;
 
 	spin_lock_irqsave(&mmsys->lock, flags);
 
 	if (assert)
-		mtk_mmsys_update_bits(mmsys, mmsys->data->sw0_rst_offset, BIT(id), 0, NULL);
+		mtk_mmsys_update_bits(mmsys, mmsys->data->sw0_rst_offset + offset, BIT(id),
+				      0, NULL);
 	else
-		mtk_mmsys_update_bits(mmsys, mmsys->data->sw0_rst_offset, BIT(id), BIT(id), NULL);
+		mtk_mmsys_update_bits(mmsys, mmsys->data->sw0_rst_offset + offset, BIT(id),
+				      BIT(id), NULL);
 
 	spin_unlock_irqrestore(&mmsys->lock, flags);
 
@@ -350,18 +361,6 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
 		return ret;
 	}
 
-	spin_lock_init(&mmsys->lock);
-
-	mmsys->rcdev.owner = THIS_MODULE;
-	mmsys->rcdev.nr_resets = 32;
-	mmsys->rcdev.ops = &mtk_mmsys_reset_ops;
-	mmsys->rcdev.of_node = pdev->dev.of_node;
-	ret = devm_reset_controller_register(&pdev->dev, &mmsys->rcdev);
-	if (ret) {
-		dev_err(&pdev->dev, "Couldn't register mmsys reset controller: %d\n", ret);
-		return ret;
-	}
-
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	if (!res) {
 		dev_err(dev, "Couldn't get mmsys resource\n");
@@ -383,6 +382,18 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
 		mmsys->data = match_data->drv_data[0];
 	}
 
+	spin_lock_init(&mmsys->lock);
+
+	mmsys->rcdev.owner = THIS_MODULE;
+	mmsys->rcdev.nr_resets = mmsys->data->num_resets;
+	mmsys->rcdev.ops = &mtk_mmsys_reset_ops;
+	mmsys->rcdev.of_node = pdev->dev.of_node;
+	ret = devm_reset_controller_register(&pdev->dev, &mmsys->rcdev);
+	if (ret) {
+		dev_err(&pdev->dev, "Couldn't register mmsys reset controller: %d\n", ret);
+		return ret;
+	}
+
 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
 	ret = cmdq_dev_get_client_reg(dev, &mmsys->cmdq_base, 0);
 	if (ret)
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index f01ba206481d..20a271b80b3b 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -92,6 +92,7 @@ struct mtk_mmsys_driver_data {
 	const struct mtk_mmsys_routes *routes;
 	const unsigned int num_routes;
 	const u16 sw0_rst_offset;
+	const u32 num_resets;
 };
 
 struct mtk_mmsys_match_data {
-- 
2.18.0



  parent reply	other threads:[~2022-05-04  9:15 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-04  9:14 [PATCH v20 00/25] Add MediaTek SoC DRM (vdosys1) support for mt8195 Nancy.Lin
2022-05-04  9:14 ` [PATCH v20 01/25] dt-bindings: mediatek: add vdosys1 RDMA definition " Nancy.Lin
2022-05-04  9:14 ` [PATCH v20 02/25] dt-bindings: reset: mt8195: add vdosys1 reset control bit Nancy.Lin
2022-05-04  9:14 ` [PATCH v20 03/25] dt-bindings: mediatek: add ethdr definition for mt8195 Nancy.Lin
2022-05-04  9:14 ` [PATCH v20 04/25] soc: mediatek: add mtk-mmsys ethdr and mdp_rdma components Nancy.Lin
2022-05-04  9:14 ` [PATCH v20 05/25] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1 Nancy.Lin
2022-05-04  9:14 ` [PATCH v20 06/25] soc: mediatek: add mtk_mmsys_update_bits API Nancy.Lin
2022-05-04  9:16   ` AngeloGioacchino Del Regno
2022-05-04  9:14 ` [PATCH v20 07/25] soc: mediatek: add mtk-mmsys config API for mt8195 vdosys1 Nancy.Lin
2022-05-04  9:14 ` [PATCH v20 08/25] soc: mediatek: add cmdq support of " Nancy.Lin
2022-05-04  9:14 ` Nancy.Lin [this message]
2022-05-04  9:14 ` [PATCH v20 10/25] soc: mediatek: mmsys: add reset control for MT8195 vdosys1 Nancy.Lin
2022-05-04  9:14 ` [PATCH v20 11/25] soc: mediatek: add mtk-mutex component - dp_intf1 Nancy.Lin
2022-05-04  9:14 ` [PATCH v20 12/25] soc: mediatek: add mtk-mutex support for mt8195 vdosys1 Nancy.Lin
2022-05-04  9:14 ` [PATCH v20 13/25] drm/mediatek: add display MDP RDMA support for MT8195 Nancy.Lin
2022-05-04  9:14 ` [PATCH v20 14/25] drm/mediatek: add display merge advance config API " Nancy.Lin
2022-05-04  9:14 ` [PATCH v20 15/25] drm/mediatek: add display merge start/stop API for cmdq support Nancy.Lin
2022-05-04  9:14 ` [PATCH v20 16/25] drm/mediatek: add display merge mute/unmute support for MT8195 Nancy.Lin
2022-05-04  9:14 ` [PATCH v20 17/25] drm/mediatek: add display merge async reset control Nancy.Lin
2022-05-04  9:14 ` [PATCH v20 18/25] drm/mediatek: add ETHDR support for MT8195 Nancy.Lin
2022-05-04  9:14 ` [PATCH v20 19/25] drm/mediatek: add mediatek-drm plane color encoding info Nancy.Lin
2022-05-04  9:14 ` [PATCH v20 20/25] drm/mediatek: add ovl_adaptor support for MT8195 Nancy.Lin
2022-05-04  9:14 ` [PATCH v20 21/25] drm/mediatek: add dma dev get function Nancy.Lin
2022-05-04  9:14 ` [PATCH v20 22/25] drm/mediatek: modify mediatek-drm for mt8195 multi mmsys support Nancy.Lin
2022-05-04  9:14 ` [PATCH v20 23/25] drm/mediatek: add drm ovl_adaptor sub driver for MT8195 Nancy.Lin
2022-05-04  9:14 ` [PATCH v20 24/25] drm/mediatek: add mediatek-drm of vdosys1 support " Nancy.Lin
2022-05-04  9:14 ` [PATCH v20 25/25] arm64: dts: mt8195: add display node for vdosys1 Nancy.Lin

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