From: Nancy.Lin <[email protected]>
To: Rob Herring <[email protected]>,
Matthias Brugger <[email protected]>,
Chun-Kuang Hu <[email protected]>,
"Philipp Zabel" <[email protected]>,
<[email protected]>,
"AngeloGioacchino Del Regno"
<[email protected]>, <[email protected]>
Cc: [email protected],
[email protected],
Yongqiang Niu <[email protected]>,
David Airlie <[email protected]>,
"jason-jh . lin" <[email protected]>,
[email protected], [email protected],
Nick Desaulniers <[email protected]>,
[email protected], [email protected],
Nathan Chancellor <[email protected]>,
"Nancy . Lin" <[email protected]>,
[email protected],
[email protected]
Subject: [PATCH v20 05/25] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1
Date: Wed, 4 May 2022 17:14:20 +0800 [thread overview]
Message-ID: <[email protected]> (raw)
In-Reply-To: <[email protected]>
Add mt8195 vdosys1 routing table to the driver data of mtk-mmsys.
Signed-off-by: Nancy.Lin <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Reviewed-by: Rex-BC Chen <[email protected]>
Reviewed-by: CK Hu <[email protected]>
---
drivers/soc/mediatek/mt8195-mmsys.h | 139 ++++++++++++++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.c | 2 +
2 files changed, 141 insertions(+)
diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
index abfe94a30248..fd7b455bd675 100644
--- a/drivers/soc/mediatek/mt8195-mmsys.h
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -75,6 +75,70 @@
#define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 (2 << 16)
#define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE (3 << 16)
+#define MT8195_VDO1_VPP_MERGE0_P0_SEL_IN 0xf04
+#define MT8195_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0 1
+
+#define MT8195_VDO1_VPP_MERGE0_P1_SEL_IN 0xf08
+#define MT8195_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1 1
+
+#define MT8195_VDO1_DISP_DPI1_SEL_IN 0xf10
+#define MT8195_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT 0
+
+#define MT8195_VDO1_DISP_DP_INTF0_SEL_IN 0xf14
+#define MT8195_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT 0
+
+#define MT8195_VDO1_MERGE4_SOUT_SEL 0xf18
+#define MT8195_MERGE4_SOUT_TO_DPI1_SEL 2
+#define MT8195_MERGE4_SOUT_TO_DP_INTF0_SEL 3
+
+#define MT8195_VDO1_MIXER_IN1_SEL_IN 0xf24
+#define MT8195_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT 1
+
+#define MT8195_VDO1_MIXER_IN2_SEL_IN 0xf28
+#define MT8195_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT 1
+
+#define MT8195_VDO1_MIXER_IN3_SEL_IN 0xf2c
+#define MT8195_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT 1
+
+#define MT8195_VDO1_MIXER_IN4_SEL_IN 0xf30
+#define MT8195_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT 1
+
+#define MT8195_VDO1_MIXER_OUT_SOUT_SEL 0xf34
+#define MT8195_MIXER_SOUT_TO_MERGE4_ASYNC_SEL 1
+
+#define MT8195_VDO1_VPP_MERGE1_P0_SEL_IN 0xf3c
+#define MT8195_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2 1
+
+#define MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL 0xf40
+#define MT8195_SOUT_TO_MIXER_IN1_SEL 1
+
+#define MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL 0xf44
+#define MT8195_SOUT_TO_MIXER_IN2_SEL 1
+
+#define MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL 0xf48
+#define MT8195_SOUT_TO_MIXER_IN3_SEL 1
+
+#define MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL 0xf4c
+#define MT8195_SOUT_TO_MIXER_IN4_SEL 1
+
+#define MT8195_VDO1_MERGE4_ASYNC_SEL_IN 0xf50
+#define MT8195_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT 1
+
+#define MT8195_VDO1_MIXER_IN1_SOUT_SEL 0xf58
+#define MT8195_MIXER_IN1_SOUT_TO_DISP_MIXER 0
+
+#define MT8195_VDO1_MIXER_IN2_SOUT_SEL 0xf5c
+#define MT8195_MIXER_IN2_SOUT_TO_DISP_MIXER 0
+
+#define MT8195_VDO1_MIXER_IN3_SOUT_SEL 0xf60
+#define MT8195_MIXER_IN3_SOUT_TO_DISP_MIXER 0
+
+#define MT8195_VDO1_MIXER_IN4_SOUT_SEL 0xf64
+#define MT8195_MIXER_IN4_SOUT_TO_DISP_MIXER 0
+
+#define MT8195_VDO1_MIXER_SOUT_SEL_IN 0xf68
+#define MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER 0
+
static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
{
DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
@@ -367,4 +431,79 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
}
};
+static const struct mtk_mmsys_routes mmsys_mt8195_vdo1_routing_table[] = {
+ {
+ DDP_COMPONENT_MDP_RDMA0, DDP_COMPONENT_MERGE1,
+ MT8195_VDO1_VPP_MERGE0_P0_SEL_IN, GENMASK(0, 0),
+ MT8195_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0
+ }, {
+ DDP_COMPONENT_MDP_RDMA1, DDP_COMPONENT_MERGE1,
+ MT8195_VDO1_VPP_MERGE0_P1_SEL_IN, GENMASK(0, 0),
+ MT8195_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1
+ }, {
+ DDP_COMPONENT_MDP_RDMA2, DDP_COMPONENT_MERGE2,
+ MT8195_VDO1_VPP_MERGE1_P0_SEL_IN, GENMASK(0, 0),
+ MT8195_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2
+ }, {
+ DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER,
+ MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL, GENMASK(1, 0),
+ MT8195_SOUT_TO_MIXER_IN1_SEL
+ }, {
+ DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER,
+ MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL, GENMASK(1, 0),
+ MT8195_SOUT_TO_MIXER_IN2_SEL
+ }, {
+ DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER,
+ MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL, GENMASK(1, 0),
+ MT8195_SOUT_TO_MIXER_IN3_SEL
+ }, {
+ DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER,
+ MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL, GENMASK(1, 0),
+ MT8195_SOUT_TO_MIXER_IN4_SEL
+ }, {
+ DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_OUT_SOUT_SEL, GENMASK(0, 0),
+ MT8195_MIXER_SOUT_TO_MERGE4_ASYNC_SEL
+ }, {
+ DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER,
+ MT8195_VDO1_MIXER_IN1_SEL_IN, GENMASK(0, 0),
+ MT8195_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT
+ }, {
+ DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER,
+ MT8195_VDO1_MIXER_IN2_SEL_IN, GENMASK(0, 0),
+ MT8195_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT
+ }, {
+ DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER,
+ MT8195_VDO1_MIXER_IN3_SEL_IN, GENMASK(0, 0),
+ MT8195_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT
+ }, {
+ DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER,
+ MT8195_VDO1_MIXER_IN4_SEL_IN, GENMASK(0, 0),
+ MT8195_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT
+ }, {
+ DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_SOUT_SEL_IN, GENMASK(2, 0),
+ MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER
+ }, {
+ DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MERGE4_ASYNC_SEL_IN, GENMASK(2, 0),
+ MT8195_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT
+ }, {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
+ MT8195_VDO1_DISP_DPI1_SEL_IN, GENMASK(1, 0),
+ MT8195_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT
+ }, {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
+ MT8195_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0),
+ MT8195_MERGE4_SOUT_TO_DPI1_SEL
+ }, {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
+ MT8195_VDO1_DISP_DP_INTF0_SEL_IN, GENMASK(1, 0),
+ MT8195_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT
+ }, {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
+ MT8195_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0),
+ MT8195_MERGE4_SOUT_TO_DP_INTF0_SEL
+ }
+};
#endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 548efed8dc1c..ab3c5cbb0175 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -146,6 +146,8 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
.io_start = 0x1c100000,
.clk_driver = "clk-mt8195-vdo1",
+ .routes = mmsys_mt8195_vdo1_routing_table,
+ .num_routes = ARRAY_SIZE(mmsys_mt8195_vdo1_routing_table),
};
static const struct mtk_mmsys_match_data mt8195_mmsys_match_data = {
--
2.18.0
next prev parent reply other threads:[~2022-05-04 9:14 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-04 9:14 [PATCH v20 00/25] Add MediaTek SoC DRM (vdosys1) support for mt8195 Nancy.Lin
2022-05-04 9:14 ` [PATCH v20 01/25] dt-bindings: mediatek: add vdosys1 RDMA definition " Nancy.Lin
2022-05-04 9:14 ` [PATCH v20 02/25] dt-bindings: reset: mt8195: add vdosys1 reset control bit Nancy.Lin
2022-05-04 9:14 ` [PATCH v20 03/25] dt-bindings: mediatek: add ethdr definition for mt8195 Nancy.Lin
2022-05-04 9:14 ` [PATCH v20 04/25] soc: mediatek: add mtk-mmsys ethdr and mdp_rdma components Nancy.Lin
2022-05-04 9:14 ` Nancy.Lin [this message]
2022-05-04 9:14 ` [PATCH v20 06/25] soc: mediatek: add mtk_mmsys_update_bits API Nancy.Lin
2022-05-04 9:16 ` AngeloGioacchino Del Regno
2022-05-04 9:14 ` [PATCH v20 07/25] soc: mediatek: add mtk-mmsys config API for mt8195 vdosys1 Nancy.Lin
2022-05-04 9:14 ` [PATCH v20 08/25] soc: mediatek: add cmdq support of " Nancy.Lin
2022-05-04 9:14 ` [PATCH v20 09/25] soc: mediatek: mmsys: add mmsys for support 64 reset bits Nancy.Lin
2022-05-04 9:14 ` [PATCH v20 10/25] soc: mediatek: mmsys: add reset control for MT8195 vdosys1 Nancy.Lin
2022-05-04 9:14 ` [PATCH v20 11/25] soc: mediatek: add mtk-mutex component - dp_intf1 Nancy.Lin
2022-05-04 9:14 ` [PATCH v20 12/25] soc: mediatek: add mtk-mutex support for mt8195 vdosys1 Nancy.Lin
2022-05-04 9:14 ` [PATCH v20 13/25] drm/mediatek: add display MDP RDMA support for MT8195 Nancy.Lin
2022-05-04 9:14 ` [PATCH v20 14/25] drm/mediatek: add display merge advance config API " Nancy.Lin
2022-05-04 9:14 ` [PATCH v20 15/25] drm/mediatek: add display merge start/stop API for cmdq support Nancy.Lin
2022-05-04 9:14 ` [PATCH v20 16/25] drm/mediatek: add display merge mute/unmute support for MT8195 Nancy.Lin
2022-05-04 9:14 ` [PATCH v20 17/25] drm/mediatek: add display merge async reset control Nancy.Lin
2022-05-04 9:14 ` [PATCH v20 18/25] drm/mediatek: add ETHDR support for MT8195 Nancy.Lin
2022-05-04 9:14 ` [PATCH v20 19/25] drm/mediatek: add mediatek-drm plane color encoding info Nancy.Lin
2022-05-04 9:14 ` [PATCH v20 20/25] drm/mediatek: add ovl_adaptor support for MT8195 Nancy.Lin
2022-05-04 9:14 ` [PATCH v20 21/25] drm/mediatek: add dma dev get function Nancy.Lin
2022-05-04 9:14 ` [PATCH v20 22/25] drm/mediatek: modify mediatek-drm for mt8195 multi mmsys support Nancy.Lin
2022-05-04 9:14 ` [PATCH v20 23/25] drm/mediatek: add drm ovl_adaptor sub driver for MT8195 Nancy.Lin
2022-05-04 9:14 ` [PATCH v20 24/25] drm/mediatek: add mediatek-drm of vdosys1 support " Nancy.Lin
2022-05-04 9:14 ` [PATCH v20 25/25] arm64: dts: mt8195: add display node for vdosys1 Nancy.Lin
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