[ammarfaizi2-block:broonie/sound/for-next 322/353] sound/soc/fsl/fsl_utils.c:125:31: sparse: sparse: Using plain integer as NULL pointer

[kernel test robot <lkp@intel.com>]

Hi Shengjiu,

First bad commit (maybe != root cause):

tree:   https://github.com/ammarfaizi2/linux-block broonie/sound/for-next
head:   3f4322bb413adb7f9d8b5e9005eb1b9bc85f9312
commit: 93f54100fbdedc22e8d88d037a8a3e32101724eb [322/353] ASoC: fsl_micfil: Add support for PLL switch at runtime
config: powerpc-randconfig-s031-20220706 (https://download.01.org/0day-ci/archive/20220707/202207070521.JjRAUeas-lkp@intel.com/config)
compiler: powerpc-linux-gcc (GCC) 11.3.0
reproduce:
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # apt-get install sparse
        # sparse version: v0.6.4-39-gce1a6720-dirty
        # https://github.com/ammarfaizi2/linux-block/commit/93f54100fbdedc22e8d88d037a8a3e32101724eb
        git remote add ammarfaizi2-block https://github.com/ammarfaizi2/linux-block
        git fetch --no-tags ammarfaizi2-block broonie/sound/for-next
        git checkout 93f54100fbdedc22e8d88d037a8a3e32101724eb
        # save the config file
        mkdir build_dir && cp config build_dir/.config
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.3.0 make.cross C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' O=build_dir ARCH=powerpc SHELL=/bin/bash sound/soc/fsl/

If you fix the issue, kindly add following tag where applicable
Reported-by: kernel test robot <lkp@intel.com>


sparse warnings: (new ones prefixed by >>)
>> sound/soc/fsl/fsl_utils.c:125:31: sparse: sparse: Using plain integer as NULL pointer
   sound/soc/fsl/fsl_utils.c:125:42: sparse: sparse: Using plain integer as NULL pointer

vim +125 sound/soc/fsl/fsl_utils.c

7bad8125549cda Shengjiu Wang 2022-07-01  109  
7bad8125549cda Shengjiu Wang 2022-07-01  110  /**
7bad8125549cda Shengjiu Wang 2022-07-01  111   * fsl_asoc_reparent_pll_clocks - set clock parent if necessary
7bad8125549cda Shengjiu Wang 2022-07-01  112   *
7bad8125549cda Shengjiu Wang 2022-07-01  113   * @dev: device pointer
7bad8125549cda Shengjiu Wang 2022-07-01  114   * @clk: root clock pointer
7bad8125549cda Shengjiu Wang 2022-07-01  115   * @pll8k_clk: PLL clock pointer for 8kHz
7bad8125549cda Shengjiu Wang 2022-07-01  116   * @pll11k_clk: PLL clock pointer for 11kHz
7bad8125549cda Shengjiu Wang 2022-07-01  117   * @ratio: target requency for root clock
7bad8125549cda Shengjiu Wang 2022-07-01  118   *
7bad8125549cda Shengjiu Wang 2022-07-01  119   * This function set root clock parent according to the target ratio
7bad8125549cda Shengjiu Wang 2022-07-01  120   */
7bad8125549cda Shengjiu Wang 2022-07-01  121  void fsl_asoc_reparent_pll_clocks(struct device *dev, struct clk *clk,
7bad8125549cda Shengjiu Wang 2022-07-01  122  				  struct clk *pll8k_clk,
7bad8125549cda Shengjiu Wang 2022-07-01  123  				  struct clk *pll11k_clk, u64 ratio)
7bad8125549cda Shengjiu Wang 2022-07-01  124  {
7bad8125549cda Shengjiu Wang 2022-07-01 @125  	struct clk *p, *pll = 0, *npll = 0;
7bad8125549cda Shengjiu Wang 2022-07-01  126  	bool reparent = false;
7bad8125549cda Shengjiu Wang 2022-07-01  127  	int ret = 0;
7bad8125549cda Shengjiu Wang 2022-07-01  128  
7bad8125549cda Shengjiu Wang 2022-07-01  129  	if (!clk || !pll8k_clk || !pll11k_clk)
7bad8125549cda Shengjiu Wang 2022-07-01  130  		return;
7bad8125549cda Shengjiu Wang 2022-07-01  131  
7bad8125549cda Shengjiu Wang 2022-07-01  132  	p = clk;
7bad8125549cda Shengjiu Wang 2022-07-01  133  	while (p && pll8k_clk && pll11k_clk) {
7bad8125549cda Shengjiu Wang 2022-07-01  134  		struct clk *pp = clk_get_parent(p);
7bad8125549cda Shengjiu Wang 2022-07-01  135  
7bad8125549cda Shengjiu Wang 2022-07-01  136  		if (clk_is_match(pp, pll8k_clk) ||
7bad8125549cda Shengjiu Wang 2022-07-01  137  		    clk_is_match(pp, pll11k_clk)) {
7bad8125549cda Shengjiu Wang 2022-07-01  138  			pll = pp;
7bad8125549cda Shengjiu Wang 2022-07-01  139  			break;
7bad8125549cda Shengjiu Wang 2022-07-01  140  		}
7bad8125549cda Shengjiu Wang 2022-07-01  141  		p = pp;
7bad8125549cda Shengjiu Wang 2022-07-01  142  	}
7bad8125549cda Shengjiu Wang 2022-07-01  143  
7bad8125549cda Shengjiu Wang 2022-07-01  144  	npll = (do_div(ratio, 8000) ? pll11k_clk : pll8k_clk);
7bad8125549cda Shengjiu Wang 2022-07-01  145  	reparent = (pll && !clk_is_match(pll, npll));
7bad8125549cda Shengjiu Wang 2022-07-01  146  
7bad8125549cda Shengjiu Wang 2022-07-01  147  	if (reparent) {
7bad8125549cda Shengjiu Wang 2022-07-01  148  		ret = clk_set_parent(p, npll);
7bad8125549cda Shengjiu Wang 2022-07-01  149  		if (ret < 0)
7bad8125549cda Shengjiu Wang 2022-07-01  150  			dev_warn(dev, "failed to set parent %s: %d\n", __clk_get_name(npll), ret);
7bad8125549cda Shengjiu Wang 2022-07-01  151  	}
7bad8125549cda Shengjiu Wang 2022-07-01  152  }
7bad8125549cda Shengjiu Wang 2022-07-01  153  EXPORT_SYMBOL(fsl_asoc_reparent_pll_clocks);
7bad8125549cda Shengjiu Wang 2022-07-01  154  

:::::: The code at line 125 was first introduced by commit
:::::: 7bad8125549cda14d9ccf97d7d76f7ef6ac9d206 ASoC: fsl_utils: Add function to handle PLL clock source

:::::: TO: Shengjiu Wang <shengjiu.wang@nxp.com>
:::::: CC: Mark Brown <broonie@kernel.org>

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