tree: https://github.com/ammarfaizi2/linux-block tglx/devel/devmsi head: 78098b3d1f7f59d8389a818e91a742ccc5caa500 commit: 6658dec9caea7fdbd07b5e87b48b8dc55e66d75c [23/89] PCI/MSI: Move pci_alloc_irq_vectors() to api.c config: arm-buildonly-randconfig-r001-20221108 compiler: clang version 16.0.0 (https://github.com/llvm/llvm-project 7aa90b21b453d1ca52fdfccfd7e01e61d9e5b1f1) reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # install arm cross compiling tool for clang build # apt-get install binutils-arm-linux-gnueabi # https://github.com/ammarfaizi2/linux-block/commit/6658dec9caea7fdbd07b5e87b48b8dc55e66d75c git remote add ammarfaizi2-block https://github.com/ammarfaizi2/linux-block git fetch --no-tags ammarfaizi2-block tglx/devel/devmsi git checkout 6658dec9caea7fdbd07b5e87b48b8dc55e66d75c # save the config file mkdir build_dir && cp config build_dir/.config COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=arm SHELL=/bin/bash drivers/crypto/inside-secure/ If you fix the issue, kindly add following tag where applicable | Reported-by: kernel test robot All errors (new ones prefixed by >>): >> drivers/crypto/inside-secure/safexcel.c:1607:9: error: call to undeclared function 'pci_alloc_irq_vectors'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] ret = pci_alloc_irq_vectors(pci_pdev, ^ drivers/crypto/inside-secure/safexcel.c:1607:9: note: did you mean 'pci_irq_vector'? include/linux/pci.h:1898:19: note: 'pci_irq_vector' declared here static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr) ^ drivers/crypto/inside-secure/safexcel.c:1772:39: warning: shift count >= width of type [-Wshift-count-overflow] ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); ^~~~~~~~~~~~~~~~ include/linux/dma-mapping.h:76:54: note: expanded from macro 'DMA_BIT_MASK' #define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1)) ^ ~~~ 1 warning and 1 error generated. vim +/pci_alloc_irq_vectors +1607 drivers/crypto/inside-secure/safexcel.c 871df319bd48ac Antoine Tenart 2017-12-14 1389 625f269a5a7a36 Pascal van Leeuwen 2019-08-19 1390 /* 625f269a5a7a36 Pascal van Leeuwen 2019-08-19 1391 * Generic part of probe routine, shared by platform and PCI driver 625f269a5a7a36 Pascal van Leeuwen 2019-08-19 1392 * 625f269a5a7a36 Pascal van Leeuwen 2019-08-19 1393 * Assumes IO resources have been mapped, private data mem has been allocated, 625f269a5a7a36 Pascal van Leeuwen 2019-08-19 1394 * clocks have been enabled, device pointer has been assigned etc. 625f269a5a7a36 Pascal van Leeuwen 2019-08-19 1395 * 625f269a5a7a36 Pascal van Leeuwen 2019-08-19 1396 */ 625f269a5a7a36 Pascal van Leeuwen 2019-08-19 1397 static int safexcel_probe_generic(void *pdev, 625f269a5a7a36 Pascal van Leeuwen 2019-08-19 1398 struct safexcel_crypto_priv *priv, 625f269a5a7a36 Pascal van Leeuwen 2019-08-19 1399 int is_pci_dev) 1b44c5a60c137e Antoine Tenart 2017-05-24 1400 { 625f269a5a7a36 Pascal van Leeuwen 2019-08-19 1401 struct device *dev = priv->dev; 5fd39c4d96c9bc Pascal van Leeuwen 2019-09-18 1402 u32 peid, version, mask, val, hiaopt, hwopt, peopt; 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1403 int i, ret, hwctg; 1b44c5a60c137e Antoine Tenart 2017-05-24 1404 625f269a5a7a36 Pascal van Leeuwen 2019-08-19 1405 priv->context_pool = dmam_pool_create("safexcel-context", dev, 625f269a5a7a36 Pascal van Leeuwen 2019-08-19 1406 sizeof(struct safexcel_context_record), 625f269a5a7a36 Pascal van Leeuwen 2019-08-19 1407 1, 0); 625f269a5a7a36 Pascal van Leeuwen 2019-08-19 1408 if (!priv->context_pool) 1b44c5a60c137e Antoine Tenart 2017-05-24 1409 return -ENOMEM; 1b44c5a60c137e Antoine Tenart 2017-05-24 1410 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1411 /* 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1412 * First try the EIP97 HIA version regs 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1413 * For the EIP197, this is guaranteed to NOT return any of the test 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1414 * values 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1415 */ 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1416 version = readl(priv->base + EIP97_HIA_AIC_BASE + EIP197_HIA_VERSION); 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1417 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1418 mask = 0; /* do not swap */ 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1419 if (EIP197_REG_LO16(version) == EIP197_HIA_VERSION_LE) { 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1420 priv->hwconfig.hiaver = EIP197_VERSION_MASK(version); 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1421 } else if (EIP197_REG_HI16(version) == EIP197_HIA_VERSION_BE) { 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1422 /* read back byte-swapped, so complement byte swap bits */ 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1423 mask = EIP197_MST_CTRL_BYTE_SWAP_BITS; 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1424 priv->hwconfig.hiaver = EIP197_VERSION_SWAP(version); 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1425 } else { 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1426 /* So it wasn't an EIP97 ... maybe it's an EIP197? */ 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1427 version = readl(priv->base + EIP197_HIA_AIC_BASE + 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1428 EIP197_HIA_VERSION); 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1429 if (EIP197_REG_LO16(version) == EIP197_HIA_VERSION_LE) { 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1430 priv->hwconfig.hiaver = EIP197_VERSION_MASK(version); 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1431 priv->flags |= SAFEXCEL_HW_EIP197; 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1432 } else if (EIP197_REG_HI16(version) == 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1433 EIP197_HIA_VERSION_BE) { 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1434 /* read back byte-swapped, so complement swap bits */ 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1435 mask = EIP197_MST_CTRL_BYTE_SWAP_BITS; 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1436 priv->hwconfig.hiaver = EIP197_VERSION_SWAP(version); 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1437 priv->flags |= SAFEXCEL_HW_EIP197; 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1438 } else { 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1439 return -ENODEV; 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1440 } 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1441 } 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1442 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1443 /* Now initialize the reg offsets based on the probing info so far */ 871df319bd48ac Antoine Tenart 2017-12-14 1444 safexcel_init_register_offsets(priv); 1b44c5a60c137e Antoine Tenart 2017-05-24 1445 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1446 /* 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1447 * If the version was read byte-swapped, we need to flip the device 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1448 * swapping Keep in mind here, though, that what we write will also be 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1449 * byte-swapped ... 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1450 */ 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1451 if (mask) { 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1452 val = readl(EIP197_HIA_AIC(priv) + EIP197_HIA_MST_CTRL); 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1453 val = val ^ (mask >> 24); /* toggle byte swap bits */ 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1454 writel(val, EIP197_HIA_AIC(priv) + EIP197_HIA_MST_CTRL); 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1455 } 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1456 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1457 /* 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1458 * We're not done probing yet! We may fall through to here if no HIA 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1459 * was found at all. So, with the endianness presumably correct now and 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1460 * the offsets setup, *really* probe for the EIP97/EIP197. 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1461 */ 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1462 version = readl(EIP197_GLOBAL(priv) + EIP197_VERSION); 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1463 if (((priv->flags & SAFEXCEL_HW_EIP197) && 5fd39c4d96c9bc Pascal van Leeuwen 2019-09-18 1464 (EIP197_REG_LO16(version) != EIP197_VERSION_LE) && 5fd39c4d96c9bc Pascal van Leeuwen 2019-09-18 1465 (EIP197_REG_LO16(version) != EIP196_VERSION_LE)) || 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1466 ((!(priv->flags & SAFEXCEL_HW_EIP197) && 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1467 (EIP197_REG_LO16(version) != EIP97_VERSION_LE)))) { 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1468 /* 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1469 * We did not find the device that matched our initial probing 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1470 * (or our initial probing failed) Report appropriate error. 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1471 */ 5fd39c4d96c9bc Pascal van Leeuwen 2019-09-18 1472 dev_err(priv->dev, "Probing for EIP97/EIP19x failed - no such device (read %08x)\n", 5fd39c4d96c9bc Pascal van Leeuwen 2019-09-18 1473 version); 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1474 return -ENODEV; 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1475 } 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1476 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1477 priv->hwconfig.hwver = EIP197_VERSION_MASK(version); 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1478 hwctg = version >> 28; 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1479 peid = version & 255; 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1480 5fd39c4d96c9bc Pascal van Leeuwen 2019-09-18 1481 /* Detect EIP206 processing pipe */ 5fd39c4d96c9bc Pascal van Leeuwen 2019-09-18 1482 version = readl(EIP197_PE(priv) + + EIP197_PE_VERSION(0)); 5fd39c4d96c9bc Pascal van Leeuwen 2019-09-18 1483 if (EIP197_REG_LO16(version) != EIP206_VERSION_LE) { 5fd39c4d96c9bc Pascal van Leeuwen 2019-09-18 1484 dev_err(priv->dev, "EIP%d: EIP206 not detected\n", peid); 5fd39c4d96c9bc Pascal van Leeuwen 2019-09-18 1485 return -ENODEV; 5fd39c4d96c9bc Pascal van Leeuwen 2019-09-18 1486 } 5fd39c4d96c9bc Pascal van Leeuwen 2019-09-18 1487 priv->hwconfig.ppver = EIP197_VERSION_MASK(version); 5fd39c4d96c9bc Pascal van Leeuwen 2019-09-18 1488 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1489 /* Detect EIP96 packet engine and version */ 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1490 version = readl(EIP197_PE(priv) + EIP197_PE_EIP96_VERSION(0)); 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1491 if (EIP197_REG_LO16(version) != EIP96_VERSION_LE) { 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1492 dev_err(dev, "EIP%d: EIP96 not detected.\n", peid); 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1493 return -ENODEV; 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1494 } 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1495 priv->hwconfig.pever = EIP197_VERSION_MASK(version); 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1496 5fd39c4d96c9bc Pascal van Leeuwen 2019-09-18 1497 hwopt = readl(EIP197_GLOBAL(priv) + EIP197_OPTIONS); 35c0e6c375ac7a Pascal van Leeuwen 2019-09-06 1498 hiaopt = readl(EIP197_HIA_AIC(priv) + EIP197_HIA_OPTIONS); 35c0e6c375ac7a Pascal van Leeuwen 2019-09-06 1499 dbc756fcf7f3b8 Pascal van Leeuwen 2020-09-11 1500 priv->hwconfig.icever = 0; dbc756fcf7f3b8 Pascal van Leeuwen 2020-09-11 1501 priv->hwconfig.ocever = 0; dbc756fcf7f3b8 Pascal van Leeuwen 2020-09-11 1502 priv->hwconfig.psever = 0; 35c0e6c375ac7a Pascal van Leeuwen 2019-09-06 1503 if (priv->flags & SAFEXCEL_HW_EIP197) { 35c0e6c375ac7a Pascal van Leeuwen 2019-09-06 1504 /* EIP197 */ 5fd39c4d96c9bc Pascal van Leeuwen 2019-09-18 1505 peopt = readl(EIP197_PE(priv) + EIP197_PE_OPTIONS(0)); 5fd39c4d96c9bc Pascal van Leeuwen 2019-09-18 1506 35c0e6c375ac7a Pascal van Leeuwen 2019-09-06 1507 priv->hwconfig.hwdataw = (hiaopt >> EIP197_HWDATAW_OFFSET) & 35c0e6c375ac7a Pascal van Leeuwen 2019-09-06 1508 EIP197_HWDATAW_MASK; 35c0e6c375ac7a Pascal van Leeuwen 2019-09-06 1509 priv->hwconfig.hwcfsize = ((hiaopt >> EIP197_CFSIZE_OFFSET) & 35c0e6c375ac7a Pascal van Leeuwen 2019-09-06 1510 EIP197_CFSIZE_MASK) + 35c0e6c375ac7a Pascal van Leeuwen 2019-09-06 1511 EIP197_CFSIZE_ADJUST; b2d92ac1c5eebc Pascal van Leeuwen 2019-09-06 1512 priv->hwconfig.hwrfsize = ((hiaopt >> EIP197_RFSIZE_OFFSET) & b2d92ac1c5eebc Pascal van Leeuwen 2019-09-06 1513 EIP197_RFSIZE_MASK) + b2d92ac1c5eebc Pascal van Leeuwen 2019-09-06 1514 EIP197_RFSIZE_ADJUST; 84ca4e54ab792b Pascal van Leeuwen 2019-09-18 1515 priv->hwconfig.hwnumpes = (hiaopt >> EIP197_N_PES_OFFSET) & 84ca4e54ab792b Pascal van Leeuwen 2019-09-18 1516 EIP197_N_PES_MASK; 84ca4e54ab792b Pascal van Leeuwen 2019-09-18 1517 priv->hwconfig.hwnumrings = (hiaopt >> EIP197_N_RINGS_OFFSET) & 84ca4e54ab792b Pascal van Leeuwen 2019-09-18 1518 EIP197_N_RINGS_MASK; 5fd39c4d96c9bc Pascal van Leeuwen 2019-09-18 1519 if (hiaopt & EIP197_HIA_OPT_HAS_PE_ARB) 5fd39c4d96c9bc Pascal van Leeuwen 2019-09-18 1520 priv->flags |= EIP197_PE_ARB; dbc756fcf7f3b8 Pascal van Leeuwen 2020-09-11 1521 if (EIP206_OPT_ICE_TYPE(peopt) == 1) { 5fd39c4d96c9bc Pascal van Leeuwen 2019-09-18 1522 priv->flags |= EIP197_ICE; dbc756fcf7f3b8 Pascal van Leeuwen 2020-09-11 1523 /* Detect ICE EIP207 class. engine and version */ dbc756fcf7f3b8 Pascal van Leeuwen 2020-09-11 1524 version = readl(EIP197_PE(priv) + dbc756fcf7f3b8 Pascal van Leeuwen 2020-09-11 1525 EIP197_PE_ICE_VERSION(0)); dbc756fcf7f3b8 Pascal van Leeuwen 2020-09-11 1526 if (EIP197_REG_LO16(version) != EIP207_VERSION_LE) { dbc756fcf7f3b8 Pascal van Leeuwen 2020-09-11 1527 dev_err(dev, "EIP%d: ICE EIP207 not detected.\n", dbc756fcf7f3b8 Pascal van Leeuwen 2020-09-11 1528 peid); dbc756fcf7f3b8 Pascal van Leeuwen 2020-09-11 1529 return -ENODEV; dbc756fcf7f3b8 Pascal van Leeuwen 2020-09-11 1530 } dbc756fcf7f3b8 Pascal van Leeuwen 2020-09-11 1531 priv->hwconfig.icever = EIP197_VERSION_MASK(version); dbc756fcf7f3b8 Pascal van Leeuwen 2020-09-11 1532 } dbc756fcf7f3b8 Pascal van Leeuwen 2020-09-11 1533 if (EIP206_OPT_OCE_TYPE(peopt) == 1) { dbc756fcf7f3b8 Pascal van Leeuwen 2020-09-11 1534 priv->flags |= EIP197_OCE; dbc756fcf7f3b8 Pascal van Leeuwen 2020-09-11 1535 /* Detect EIP96PP packet stream editor and version */ dbc756fcf7f3b8 Pascal van Leeuwen 2020-09-11 1536 version = readl(EIP197_PE(priv) + EIP197_PE_PSE_VERSION(0)); dbc756fcf7f3b8 Pascal van Leeuwen 2020-09-11 1537 if (EIP197_REG_LO16(version) != EIP96_VERSION_LE) { dbc756fcf7f3b8 Pascal van Leeuwen 2020-09-11 1538 dev_err(dev, "EIP%d: EIP96PP not detected.\n", peid); dbc756fcf7f3b8 Pascal van Leeuwen 2020-09-11 1539 return -ENODEV; dbc756fcf7f3b8 Pascal van Leeuwen 2020-09-11 1540 } dbc756fcf7f3b8 Pascal van Leeuwen 2020-09-11 1541 priv->hwconfig.psever = EIP197_VERSION_MASK(version); dbc756fcf7f3b8 Pascal van Leeuwen 2020-09-11 1542 /* Detect OCE EIP207 class. engine and version */ dbc756fcf7f3b8 Pascal van Leeuwen 2020-09-11 1543 version = readl(EIP197_PE(priv) + dbc756fcf7f3b8 Pascal van Leeuwen 2020-09-11 1544 EIP197_PE_ICE_VERSION(0)); dbc756fcf7f3b8 Pascal van Leeuwen 2020-09-11 1545 if (EIP197_REG_LO16(version) != EIP207_VERSION_LE) { dbc756fcf7f3b8 Pascal van Leeuwen 2020-09-11 1546 dev_err(dev, "EIP%d: OCE EIP207 not detected.\n", dbc756fcf7f3b8 Pascal van Leeuwen 2020-09-11 1547 peid); dbc756fcf7f3b8 Pascal van Leeuwen 2020-09-11 1548 return -ENODEV; dbc756fcf7f3b8 Pascal van Leeuwen 2020-09-11 1549 } dbc756fcf7f3b8 Pascal van Leeuwen 2020-09-11 1550 priv->hwconfig.ocever = EIP197_VERSION_MASK(version); dbc756fcf7f3b8 Pascal van Leeuwen 2020-09-11 1551 } 5fd39c4d96c9bc Pascal van Leeuwen 2019-09-18 1552 /* If not a full TRC, then assume simple TRC */ 5fd39c4d96c9bc Pascal van Leeuwen 2019-09-18 1553 if (!(hwopt & EIP197_OPT_HAS_TRC)) 5fd39c4d96c9bc Pascal van Leeuwen 2019-09-18 1554 priv->flags |= EIP197_SIMPLE_TRC; 5fd39c4d96c9bc Pascal van Leeuwen 2019-09-18 1555 /* EIP197 always has SOME form of TRC */ 5fd39c4d96c9bc Pascal van Leeuwen 2019-09-18 1556 priv->flags |= EIP197_TRC_CACHE; 35c0e6c375ac7a Pascal van Leeuwen 2019-09-06 1557 } else { 35c0e6c375ac7a Pascal van Leeuwen 2019-09-06 1558 /* EIP97 */ 35c0e6c375ac7a Pascal van Leeuwen 2019-09-06 1559 priv->hwconfig.hwdataw = (hiaopt >> EIP197_HWDATAW_OFFSET) & 35c0e6c375ac7a Pascal van Leeuwen 2019-09-06 1560 EIP97_HWDATAW_MASK; 35c0e6c375ac7a Pascal van Leeuwen 2019-09-06 1561 priv->hwconfig.hwcfsize = (hiaopt >> EIP97_CFSIZE_OFFSET) & 35c0e6c375ac7a Pascal van Leeuwen 2019-09-06 1562 EIP97_CFSIZE_MASK; b2d92ac1c5eebc Pascal van Leeuwen 2019-09-06 1563 priv->hwconfig.hwrfsize = (hiaopt >> EIP97_RFSIZE_OFFSET) & b2d92ac1c5eebc Pascal van Leeuwen 2019-09-06 1564 EIP97_RFSIZE_MASK; 84ca4e54ab792b Pascal van Leeuwen 2019-09-18 1565 priv->hwconfig.hwnumpes = 1; /* by definition */ 84ca4e54ab792b Pascal van Leeuwen 2019-09-18 1566 priv->hwconfig.hwnumrings = (hiaopt >> EIP197_N_RINGS_OFFSET) & 84ca4e54ab792b Pascal van Leeuwen 2019-09-18 1567 EIP197_N_RINGS_MASK; 35c0e6c375ac7a Pascal van Leeuwen 2019-09-06 1568 } 35c0e6c375ac7a Pascal van Leeuwen 2019-09-06 1569 946a4a2a49195e Pascal van Leeuwen 2019-09-18 1570 /* Scan for ring AIC's */ 946a4a2a49195e Pascal van Leeuwen 2019-09-18 1571 for (i = 0; i < EIP197_MAX_RING_AIC; i++) { 946a4a2a49195e Pascal van Leeuwen 2019-09-18 1572 version = readl(EIP197_HIA_AIC_R(priv) + 946a4a2a49195e Pascal van Leeuwen 2019-09-18 1573 EIP197_HIA_AIC_R_VERSION(i)); 946a4a2a49195e Pascal van Leeuwen 2019-09-18 1574 if (EIP197_REG_LO16(version) != EIP201_VERSION_LE) 946a4a2a49195e Pascal van Leeuwen 2019-09-18 1575 break; 946a4a2a49195e Pascal van Leeuwen 2019-09-18 1576 } 946a4a2a49195e Pascal van Leeuwen 2019-09-18 1577 priv->hwconfig.hwnumraic = i; 5fd39c4d96c9bc Pascal van Leeuwen 2019-09-18 1578 /* Low-end EIP196 may not have any ring AIC's ... */ 5fd39c4d96c9bc Pascal van Leeuwen 2019-09-18 1579 if (!priv->hwconfig.hwnumraic) { 5fd39c4d96c9bc Pascal van Leeuwen 2019-09-18 1580 dev_err(priv->dev, "No ring interrupt controller present!\n"); 5fd39c4d96c9bc Pascal van Leeuwen 2019-09-18 1581 return -ENODEV; 5fd39c4d96c9bc Pascal van Leeuwen 2019-09-18 1582 } 946a4a2a49195e Pascal van Leeuwen 2019-09-18 1583 062b64ca6db409 Pascal van Leeuwen 2019-08-30 1584 /* Get supported algorithms from EIP96 transform engine */ 062b64ca6db409 Pascal van Leeuwen 2019-08-30 1585 priv->hwconfig.algo_flags = readl(EIP197_PE(priv) + 062b64ca6db409 Pascal van Leeuwen 2019-08-30 1586 EIP197_PE_EIP96_OPTIONS(0)); 062b64ca6db409 Pascal van Leeuwen 2019-08-30 1587 118db42deeeff1 Pascal van Leeuwen 2019-09-06 1588 /* Print single info line describing what we just detected */ dbc756fcf7f3b8 Pascal van Leeuwen 2020-09-11 1589 dev_info(priv->dev, "EIP%d:%x(%d,%d,%d,%d)-HIA:%x(%d,%d,%d),PE:%x/%x(alg:%08x)/%x/%x/%x\n", 84ca4e54ab792b Pascal van Leeuwen 2019-09-18 1590 peid, priv->hwconfig.hwver, hwctg, priv->hwconfig.hwnumpes, 946a4a2a49195e Pascal van Leeuwen 2019-09-18 1591 priv->hwconfig.hwnumrings, priv->hwconfig.hwnumraic, 946a4a2a49195e Pascal van Leeuwen 2019-09-18 1592 priv->hwconfig.hiaver, priv->hwconfig.hwdataw, 946a4a2a49195e Pascal van Leeuwen 2019-09-18 1593 priv->hwconfig.hwcfsize, priv->hwconfig.hwrfsize, 5fd39c4d96c9bc Pascal van Leeuwen 2019-09-18 1594 priv->hwconfig.ppver, priv->hwconfig.pever, dbc756fcf7f3b8 Pascal van Leeuwen 2020-09-11 1595 priv->hwconfig.algo_flags, priv->hwconfig.icever, dbc756fcf7f3b8 Pascal van Leeuwen 2020-09-11 1596 priv->hwconfig.ocever, priv->hwconfig.psever); 1b44c5a60c137e Antoine Tenart 2017-05-24 1597 625f269a5a7a36 Pascal van Leeuwen 2019-08-19 1598 safexcel_configure(priv); 5b37689653cbe7 Gregory CLEMENT 2018-03-13 1599 625f269a5a7a36 Pascal van Leeuwen 2019-08-19 1600 if (IS_ENABLED(CONFIG_PCI) && priv->version == EIP197_DEVBRD) { 625f269a5a7a36 Pascal van Leeuwen 2019-08-19 1601 /* 625f269a5a7a36 Pascal van Leeuwen 2019-08-19 1602 * Request MSI vectors for global + 1 per ring - 625f269a5a7a36 Pascal van Leeuwen 2019-08-19 1603 * or just 1 for older dev images 625f269a5a7a36 Pascal van Leeuwen 2019-08-19 1604 */ 625f269a5a7a36 Pascal van Leeuwen 2019-08-19 1605 struct pci_dev *pci_pdev = pdev; 625f269a5a7a36 Pascal van Leeuwen 2019-08-19 1606 625f269a5a7a36 Pascal van Leeuwen 2019-08-19 @1607 ret = pci_alloc_irq_vectors(pci_pdev, 625f269a5a7a36 Pascal van Leeuwen 2019-08-19 1608 priv->config.rings + 1, 625f269a5a7a36 Pascal van Leeuwen 2019-08-19 1609 priv->config.rings + 1, 625f269a5a7a36 Pascal van Leeuwen 2019-08-19 1610 PCI_IRQ_MSI | PCI_IRQ_MSIX); 625f269a5a7a36 Pascal van Leeuwen 2019-08-19 1611 if (ret < 0) { 625f269a5a7a36 Pascal van Leeuwen 2019-08-19 1612 dev_err(dev, "Failed to allocate PCI MSI interrupts\n"); 1b44c5a60c137e Antoine Tenart 2017-05-24 1613 return ret; 1b44c5a60c137e Antoine Tenart 2017-05-24 1614 } 1b44c5a60c137e Antoine Tenart 2017-05-24 1615 } 1b44c5a60c137e Antoine Tenart 2017-05-24 1616 625f269a5a7a36 Pascal van Leeuwen 2019-08-19 1617 /* Register the ring IRQ handlers and configure the rings */ 329e09893909d4 Kees Cook 2018-10-05 1618 priv->ring = devm_kcalloc(dev, priv->config.rings, 329e09893909d4 Kees Cook 2018-10-05 1619 sizeof(*priv->ring), 18e0e95b82e444 Ofer Heifetz 2018-06-28 1620 GFP_KERNEL); 625f269a5a7a36 Pascal van Leeuwen 2019-08-19 1621 if (!priv->ring) 625f269a5a7a36 Pascal van Leeuwen 2019-08-19 1622 return -ENOMEM; 18e0e95b82e444 Ofer Heifetz 2018-06-28 1623 1b44c5a60c137e Antoine Tenart 2017-05-24 1624 for (i = 0; i < priv->config.rings; i++) { 625f269a5a7a36 Pascal van Leeuwen 2019-08-19 1625 char wq_name[9] = {0}; 1b44c5a60c137e Antoine Tenart 2017-05-24 1626 int irq; 1b44c5a60c137e Antoine Tenart 2017-05-24 1627 struct safexcel_ring_irq_data *ring_irq; 1b44c5a60c137e Antoine Tenart 2017-05-24 1628 1b44c5a60c137e Antoine Tenart 2017-05-24 1629 ret = safexcel_init_ring_descriptors(priv, 1b44c5a60c137e Antoine Tenart 2017-05-24 1630 &priv->ring[i].cdr, 1b44c5a60c137e Antoine Tenart 2017-05-24 1631 &priv->ring[i].rdr); 625f269a5a7a36 Pascal van Leeuwen 2019-08-19 1632 if (ret) { 625f269a5a7a36 Pascal van Leeuwen 2019-08-19 1633 dev_err(dev, "Failed to initialize rings\n"); 625f269a5a7a36 Pascal van Leeuwen 2019-08-19 1634 return ret; 625f269a5a7a36 Pascal van Leeuwen 2019-08-19 1635 } 1b44c5a60c137e Antoine Tenart 2017-05-24 1636 329e09893909d4 Kees Cook 2018-10-05 1637 priv->ring[i].rdr_req = devm_kcalloc(dev, 329e09893909d4 Kees Cook 2018-10-05 1638 EIP197_DEFAULT_RING_SIZE, c98e233062cd9d Colin Ian King 2020-10-10 1639 sizeof(*priv->ring[i].rdr_req), 9744fec95f0674 Ofer Heifetz 2018-06-28 1640 GFP_KERNEL); 625f269a5a7a36 Pascal van Leeuwen 2019-08-19 1641 if (!priv->ring[i].rdr_req) 625f269a5a7a36 Pascal van Leeuwen 2019-08-19 1642 return -ENOMEM; 9744fec95f0674 Ofer Heifetz 2018-06-28 1643 1b44c5a60c137e Antoine Tenart 2017-05-24 1644 ring_irq = devm_kzalloc(dev, sizeof(*ring_irq), GFP_KERNEL); 625f269a5a7a36 Pascal van Leeuwen 2019-08-19 1645 if (!ring_irq) 625f269a5a7a36 Pascal van Leeuwen 2019-08-19 1646 return -ENOMEM; 1b44c5a60c137e Antoine Tenart 2017-05-24 1647 1b44c5a60c137e Antoine Tenart 2017-05-24 1648 ring_irq->priv = priv; 1b44c5a60c137e Antoine Tenart 2017-05-24 1649 ring_irq->ring = i; 1b44c5a60c137e Antoine Tenart 2017-05-24 1650 625f269a5a7a36 Pascal van Leeuwen 2019-08-19 1651 irq = safexcel_request_ring_irq(pdev, 625f269a5a7a36 Pascal van Leeuwen 2019-08-19 1652 EIP197_IRQ_NUMBER(i, is_pci_dev), 625f269a5a7a36 Pascal van Leeuwen 2019-08-19 1653 is_pci_dev, c6720415907f21 Sven Auhagen 2020-07-21 1654 i, 625f269a5a7a36 Pascal van Leeuwen 2019-08-19 1655 safexcel_irq_ring, 69ee4dd5ea8ce0 Antoine Tenart 2017-12-14 1656 safexcel_irq_ring_thread, 1b44c5a60c137e Antoine Tenart 2017-05-24 1657 ring_irq); b7d65fe18129e2 Christophe Jaillet 2017-08-15 1658 if (irq < 0) { 625f269a5a7a36 Pascal van Leeuwen 2019-08-19 1659 dev_err(dev, "Failed to get IRQ ID for ring %d\n", i); 625f269a5a7a36 Pascal van Leeuwen 2019-08-19 1660 return irq; b7d65fe18129e2 Christophe Jaillet 2017-08-15 1661 } 1b44c5a60c137e Antoine Tenart 2017-05-24 1662 c6720415907f21 Sven Auhagen 2020-07-21 1663 priv->ring[i].irq = irq; 1b44c5a60c137e Antoine Tenart 2017-05-24 1664 priv->ring[i].work_data.priv = priv; 1b44c5a60c137e Antoine Tenart 2017-05-24 1665 priv->ring[i].work_data.ring = i; 625f269a5a7a36 Pascal van Leeuwen 2019-08-19 1666 INIT_WORK(&priv->ring[i].work_data.work, 625f269a5a7a36 Pascal van Leeuwen 2019-08-19 1667 safexcel_dequeue_work); 1b44c5a60c137e Antoine Tenart 2017-05-24 1668 1b44c5a60c137e Antoine Tenart 2017-05-24 1669 snprintf(wq_name, 9, "wq_ring%d", i); 625f269a5a7a36 Pascal van Leeuwen 2019-08-19 1670 priv->ring[i].workqueue = 625f269a5a7a36 Pascal van Leeuwen 2019-08-19 1671 create_singlethread_workqueue(wq_name); 625f269a5a7a36 Pascal van Leeuwen 2019-08-19 1672 if (!priv->ring[i].workqueue) 625f269a5a7a36 Pascal van Leeuwen 2019-08-19 1673 return -ENOMEM; 1b44c5a60c137e Antoine Tenart 2017-05-24 1674 f7268c538b3d84 Antoine Tenart 2018-02-13 1675 priv->ring[i].requests = 0; dc7e28a3286ed4 Antoine Tenart 2017-12-14 1676 priv->ring[i].busy = false; dc7e28a3286ed4 Antoine Tenart 2017-12-14 1677 86671abbbbfc95 Antoine Tenart 2017-06-15 1678 crypto_init_queue(&priv->ring[i].queue, 86671abbbbfc95 Antoine Tenart 2017-06-15 1679 EIP197_DEFAULT_RING_SIZE); 86671abbbbfc95 Antoine Tenart 2017-06-15 1680 1b44c5a60c137e Antoine Tenart 2017-05-24 1681 spin_lock_init(&priv->ring[i].lock); 86671abbbbfc95 Antoine Tenart 2017-06-15 1682 spin_lock_init(&priv->ring[i].queue_lock); 1b44c5a60c137e Antoine Tenart 2017-05-24 1683 } 1b44c5a60c137e Antoine Tenart 2017-05-24 1684 1b44c5a60c137e Antoine Tenart 2017-05-24 1685 atomic_set(&priv->ring_used, 0); 1b44c5a60c137e Antoine Tenart 2017-05-24 1686 1b44c5a60c137e Antoine Tenart 2017-05-24 1687 ret = safexcel_hw_init(priv); 1b44c5a60c137e Antoine Tenart 2017-05-24 1688 if (ret) { 625f269a5a7a36 Pascal van Leeuwen 2019-08-19 1689 dev_err(dev, "HW init failed (%d)\n", ret); 625f269a5a7a36 Pascal van Leeuwen 2019-08-19 1690 return ret; 1b44c5a60c137e Antoine Tenart 2017-05-24 1691 } 1b44c5a60c137e Antoine Tenart 2017-05-24 1692 1b44c5a60c137e Antoine Tenart 2017-05-24 1693 ret = safexcel_register_algorithms(priv); 1b44c5a60c137e Antoine Tenart 2017-05-24 1694 if (ret) { 1b44c5a60c137e Antoine Tenart 2017-05-24 1695 dev_err(dev, "Failed to register algorithms (%d)\n", ret); 625f269a5a7a36 Pascal van Leeuwen 2019-08-19 1696 return ret; 1b44c5a60c137e Antoine Tenart 2017-05-24 1697 } 1b44c5a60c137e Antoine Tenart 2017-05-24 1698 1b44c5a60c137e Antoine Tenart 2017-05-24 1699 return 0; 1b44c5a60c137e Antoine Tenart 2017-05-24 1700 } 1b44c5a60c137e Antoine Tenart 2017-05-24 1701 :::::: The code at line 1607 was first introduced by commit :::::: 625f269a5a7a3643771320387e474bd0a61d9654 crypto: inside-secure - add support for PCI based FPGA development board :::::: TO: Pascal van Leeuwen :::::: CC: Herbert Xu -- 0-DAY CI Kernel Test Service https://01.org/lkp