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From: "H. Peter Anvin" <[email protected]>
To: David Laight <[email protected]>,
	"'Kanna Scarlet'" <[email protected]>,
	Borislav Petkov <[email protected]>
Cc: Thomas Gleixner <[email protected]>,
	Ingo Molnar <[email protected]>,
	Dave Hansen <[email protected]>,
	"[email protected]" <[email protected]>,
	Ard Biesheuvel <[email protected]>,
	Bill Metzenthen <[email protected]>,
	Brijesh Singh <[email protected]>,
	Joerg Roedel <[email protected]>,
	Josh Poimboeuf <[email protected]>,
	"Kirill A. Shutemov" <[email protected]>,
	Mark Rutland <[email protected]>,
	Michael Roth <[email protected]>,
	Peter Zijlstra <[email protected]>,
	Sean Christopherson <[email protected]>,
	Steven Rostedt <[email protected]>,
	Ammar Faizi <[email protected]>,
	GNU/Weeb Mailing List <[email protected]>,
	Linux Kernel Mailing List <[email protected]>
Subject: Re: [PATCH 1/1] x86: Change mov $0, %reg with xor %reg, %reg
Date: Mon, 8 Aug 2022 11:59:37 -0700	[thread overview]
Message-ID: <[email protected]> (raw)
In-Reply-To: <[email protected]>

On August 5, 2022 2:26:02 AM PDT, David Laight <[email protected]> 
wrote:
>From: Kanna Scarlet
>> Sent: 04 August 2022 19:08
>> 
>> On 8/4/22 10:53 PM, Borislav Petkov wrote:
>> > Bonus points if you find out what other advantage
>> >
>> > XOR reg,reg
>> >
>> > has when it comes to clearing integer registers.
>> 
>> Hello sir Borislav,
>> 
>> Thank you for your response. I tried to find out other advantages of
>> xor reg,reg on Google and found this:
>> https://stackoverflow.com/a/33668295/7275114
>> 
>>   "xor (being a recognized zeroing idiom, unlike mov reg, 0) has some
>>   obvious and some subtle advantages:
>> 
>>   1. smaller code-size than mov reg,0. (All CPUs)
>>   2. avoids partial-register penalties for later code.
>>      (Intel P6-family and SnB-family).
>>   3. doesn't use an execution unit, saving power and freeing up
>>      execution resources. (Intel SnB-family)
>>   4. smaller uop (no immediate data) leaves room in the uop cache-line
>>      for nearby instructions to borrow if needed. (Intel SnB-family).
>>   5. doesn't use up entries in the physical register file. (Intel
>>      SnB-family (and P4) at least, possibly AMD as well since they use
>>      a similar PRF design instead of keeping register state in the ROB
>>      like Intel P6-family microarchitectures.)"
>
>You missed one, and an additional change:
>
>Use "xor %rax,%rax" instead of "xor %eax,%eax" to save
>the 'reg' prefix.
>
>	David
>
>-
>Registered Address Lakeside, Bramley Road, Mount Farm, Milton Keynes, MK1 1PT, UK
>Registration No: 1397386 (Wales)
>
>

You mean the other way around...

  parent reply	other threads:[~2022-08-08 19:03 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-08-04 15:26 [PATCH 0/1] x86 change mov 0, %reg to xor %reg, %reg Kanna Scarlet
2022-08-04 15:26 ` [PATCH 1/1] x86: Change mov $0, %reg with " Kanna Scarlet
2022-08-04 15:53   ` Borislav Petkov
2022-08-04 18:08     ` Kanna Scarlet
2022-08-05  9:26       ` David Laight
2022-08-05  9:42         ` Joerg Roedel
2022-08-08 16:45           ` Kanna Scarlet
2022-08-08 18:59             ` H. Peter Anvin
2022-08-08 16:38         ` Kanna Scarlet
2022-08-08 18:59         ` H. Peter Anvin [this message]
2022-08-09  7:38           ` David Laight
2022-08-05  9:54       ` Borislav Petkov
2022-08-08 16:57         ` Kanna Scarlet

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